1. Field of Invention
The present invention is related to semiconductor memory and more particular non-volatile NAND memory arrays.
2. Description of Related Art
In F. Masuoka et al., “A New NAND Cell for Ultra High Density 5V-only EEPROMs”, May 1988, Proc 1988 Symposium on VLSI Technology, IV-5 pp33–34) a floating gate NAND cell, shown in FIG. 1A of prior art, is described that has been used widely as Non-volatile memory. Since the memory cell is placed in series without any contact, the density is very high even though the process complexity is high and the read current level is very small. The storage element in the flash NAND is a polysilicon floating gate 200 residing under a word line 201 in the example shown in FIG. 1A. The floating gate can be replaced by a nitride layer sandwiched between bottom and top oxide layers (Oxide-Nitride-Oxide) 202 laying under a word gate 201 as shown in the example in FIG. 1B and FIG. 1C of prior art. The ONO layer sandwich stores electron or hole charges in the nitride or interface trap sites as suggested in Y. Hayashi et al. “Nonvolatile Semiconductor memory and its Programming Method”, JP 11–22940, Dec. 5, 1997. This ONO storage approach for the MONOS NAND simplifies the process significantly compared to the floating gate approach. The floating gate NAND utilizes multi-level storage and provides density factor at least 2 times, whereas a the twin MONOS device of the present invention improves density by storing charges on both device edges in a single planar FET devices. In U.S. Pat. No. 5,768,192 (Eitan) a non-volatile semiconductor memory cell utilizing asymmetrical charge trapping is disclosed. However, the memory cell device suffers from a threshold shift after many program and erase cycles because the electron mean free path is larger than hole mean free path. In U.S. Pat. No. 4,943,943 (Hayashi et al.) a read-out circuit for a semiconductor nonvolatile memory is described which is capable of extracting a widely fluctuating output voltage using a reverse read.
In the present invention, the nitride storage element under the word gate is very small and well defined so that the hole injection for program is applicable over the whole nitride storage region. Erase is achieved by FN (Fowler-Norheim) electron injection, and once the nitride region is limited and optimized, then the voltage required for hole injection can be almost halved. By introducing a trap free oxide region between the two nitride storage sites, the threshold instability from program and erase cycles due to the miss match of hole and electron mean free paths is solved assuring high endurance. The voltage reduction in FN injection is achieved by reducing nitride thickness down to few atomic layers. Thus a low voltage and high density operation is achieved for the MONOS NAND structure of the present invention.